In Sharc + core, Does AWE utilize HW Accelerator IIRA for Biquad Module?
I have created 4 AWE designs which included 1(mono) to 4ch Biquad Module (stage=256) for each.
However, no reduction in MIPS of the Sharc+ core was found.
Can you show me how to use IIRA? or give some examples of AWE designs that use IIRA?
I've attached my AWE design example and its Running Profile result.
Yes, our Biquad and FIR modules utilize the hardware accelerators for MOST SHARC+ DSPs. Could you please let us know what ADI part number and AWE Core version you are using?
Thank you for your support.
I have attached information only.
Does it enough?
Your 21569 SHARC AWE Core library (v8.B.0.0) is quite old. Cross-checking the release notes, I don't think that that library utilizes the hardware accelerators. Let me email you on the side about this.